About the Beaglebone Black PinMux Modes

Summary

This page provides a discussion of the Beaglebone Black PinMux and also a listing of the usage of the various PinMux settings related to the P8 and P9 headers. The PinMux section below is clipped from the open source About the Device Tree document available from this website. The listings and downloadable quick reference pdf files (P8 Header, P9 Header) of the PinMux modes have been primarily derived from the pinmux.pdf document available on this website (and others) along with a few enhancements found in the information on Derek Molloy's informative personal website and the the documents supporting his Exploring Beaglebone resource book.

I was motivated to create an adapted version of the PinMux Mode documents because I could not find all of the information I needed on one document and was constantly referring to multiple sources. Once it was made up I thought I might as well make it generally available in the thought that it may be useful to others. If you see any mistakes or ommissions please tell me and I will make the appropriate updates.

Note: I did not write the "pinmux.pdf" document referred to above and it is not at all clear who did. The document contains no reference to an author or originating organization and it is available from multiple open source repositories on the Internet. If you know who originally compiled the information in the pinmux.pdf document please do let me know as I would like to include appropriate attribution.

About the PinMux

The CPUs of most modern microcontrollers (including the AM335x 1GHz ARM Cortex-A8 in the Beaglebone Black) are typically built to handle a multitude of requirements. For example, designers of a microcontroller board using that CPU may wish to have multiple GPIO's, SPI, I2C, PWM, A/D, HDMI, USB ports and many others. The architects of the CPU are aware of this and typically implement as many of these devices as they can just to make sure their chip gets selected for people’s designs. These types of device are called On Chip Peripherals (hence the acronym OCP) and although they are called peripherals they are actually built right onto the silicon with the CPU itself.

Each OCP device will probably require one or more physical inputs or outputs on the exterior of the CPU so that the rest of the system can interface with it. The problem with this is that, given all the OCP devices which are implemented, there are many more OCP device I/O requirements than there are pads on the exterior of the CPU.

The designers of the CPU, reasoning that most people implementing their CPU will never need to use all OCP devices at once, have implemented a rather elegant solution to the problem. They have set things up so that OCP devices share the I/O pads on the CPU. For example, the same I/O pad is alternately used by the following OCP devices: GPIO0_5, I2C1 SCL, mmc2 sdwp, SPI cs0 and others. There are up to 8 possible usages of any CPU pad and the actual usage is settable at runtime. The name for the possible usages is called the "mode" (mode0 to mode7).

Be aware of that when you read the documentation that much of the time when you see the word "pin" it is an OCP device I/O line internal to the CPU which is being referenced. It must be noted that sometimes you will see the physical pad on the CPU referred to as a "pin" and once the CPU pad has been routed out and exposed on a header block (the Beaglebone Black P8 or P9 headers for example) it is also commonly referred to as a "pin". The meaning of the word "pin" is just one of those things you have to infer from the context and which can drive you insane if you don't realize what is going on.

The internal CPU component that does the switching of OCP pins onto physical pads is called the PinMux. The PinMux configuration (and hence "pinmux mode") for all OCP devices is set by the Device Tree at boot - although it can also be dynamically adjusted later by software running in kernel mode (usually device drivers) or with Device Tree Overlays. Note that normal user mode software (even running as root) cannot adjust the PinMux mode settings.

Let's look at how the PinMux works. In concept it can be visualised as a simple switch

The PinMux can be Visualised as a Simple Rotary Switch

Of course the PinMux is not a mechanical rotary switch like that - it is all solid state on the silicon wafer of the CPU - but the effect is the same. In the example above, if you put PinMux pin 87 in mode 7 you will get GPIO0_5 present on the CPU pad A15 and this has in turn been routed out to pin 17 on the P9 header by the designers of the Beaglebone Black. If you put the PinMux pin in mode 0 then the SPI Port0 CS0 line will be present on pin 17 on the P9 header. It should be noted that not all CPU pads go to the P8 and P9 headers - some go straight to the USB ports, HDMI port or EMMC memory etc. depending on what the designers of the Beaglebone Black (not the CPU) wanted to do with them.

It is important to realize that the OCP pins which use any particular CPU pad are hard coded - really hard coded - as in burnt onto the silicon. This means that any specific OCP device must use a pre-defined set of CPU pads and this cannot be changed. If two OCP devices use the same CPU pad then you cannot enable both at the same time. You can visualize this in the above diagram by realizing that the PinMux switch cannot both point to GPIO0_5 and SPI0_CS0 at the same time.

The above reason is why you will sometimes see comments like "if you wish to use GPIO_77 you must disable the HDMI video". The reason is that both of those two OCP devices share the same PinMux pin in different modes. You simply cannot use both at once and there is no way to change this.

Note: OCP devices which are not enabled in the PinMux will still sometimes "work" in the sense that you can access them via their Device Drivers. However, if the PinMux mode is incorrect, any I/O lines that device uses will not be connected to anything.

The Beaglebone Black P8 Header PinMux Modes

The table below lists the PinMux modes for the pins exposed on the P8 Header. A downloadable and printable pdf version of this information is also available.

P8 Pin	Offset	mode0	mode1	mode2	mode3	mode4	mode5	mode6	mode7	GPIO #	P8 Pin
P8_1	GND										P8_1
P8_2	GND										P8_2
P8_3	0x818	gpmc_ad6	mmc1_dat6						gpio1_6	38	P8_3
P8_4	0x81C	gpmc_ad7	mmc1_dat7						gpio1_7	39	P8_4
P8_5	0x808	gpmc_ad2	mmc1_dat2						gpio1_2	34	P8_5
P8_6	0x80C	gpmc_ad3	mmc1_dat3						gpio1_3	35	P8_6
P8_7	0x890	gpmc_advn_ale		timer4					gpio2_2	66	P8_7
P8_8	0x894	gpmc_oen_ren		timer7					gpio2_3	67	P8_8
P8_9	0x89C	gpmc_be0n_cle		timer5					gpio2_5	69	P8_9
P8_10	0x898	gpmc_wen		timer6					gpio2_4	68	P8_10
P8_11	0x834	gpmc_ad13	lcd_data18	mmc1_dat5	mmc2_dat1	eQEP2B_in	pr1_mii0_txd1	pr1_pru0_pru_r30_15	gpio1_13	45	P8_11
P8_12	0x830	gpmc_ad12	lcd_data19	mmc1_dat4	mmc2_dat0	eQEP2A_in	pr1_mii0_txd2	pr1_pru0_pru_r30_14	gpio1_12	44	P8_12
P8_13	0x824	gpmc_ad9	lcd_data22	mmc1_dat1	mmc2_dat5	ehrpwm2B	pr1_mii0_col		gpio0_23	23	P8_13
P8_14	0x828	gpmc_ad10	lcd_data21	mmc1_dat2	mmc2_dat6	ehrpwm2_tripzone_input	pr1_mii0_txen		gpio0_26	26	P8_14
P8_15	0x83C	gpmc_ad15	lcd_data16	mmc1_dat7	mmc2_dat3	eQEP2_strobe	pr1_ecap0_ecap_capin_apwm_o	pr1_pru0_pru_r31_15	gpio1_15	47	P8_15
P8_16	0x838	gpmc_ad14	lcd_data17	mmc1_dat6	mmc2_dat2	eQEP2_index	pr1_mii0_txd0	pr1_pru0_pru_r31_14	gpio1_14	46	P8_16
P8_17	0x82C	gpmc_ad11	lcd_data20	mmc1_dat3	mmc2_dat7	ehrpwm0_synco	pr1_mii0_txd3		gpio0_27	27	P8_17
P8_18	0x88C	gpmc_clk	lcd_memory_clk	gpmc_wait1	mmc2_clk	pr1_mii1_crs	pr1_mdio_mdclk	mcasp0_fsr	gpio2_1	65	P8_18
P8_19	0x820	gpmc_ad8	lcd_data23	mmc1_dat0	mmc2_dat4	ehrpwm2A	pr1_mii_mt0_clk		gpio0_22	22	P8_19
P8_20	0x884	gpmc_csn2	gpmc_be1n	mmc1_cmd	pr1_edio_data_in7	pr1_edio_data_out7	pr1_pru1_pru_r30_13	pr1_pru1_pru_r31_13	gpio1_31	63	P8_20
P8_21	0x880	gpmc_csn1	gpmc_clk	mmc1_clk	pr1_edio_data_in6	pr1_edio_data_out6	pr1_pru1_pru_r30_12	pr1_pru1_pru_r31_12	gpio1_30	62	P8_21
P8_22	0x814	gpmc_ad5	mmc1_dat5						gpio1_5	37	P8_22
P8_23	0x810	gpmc_ad4	mmc1_dat4						gpio1_4	36	P8_23
P8_24	0x804	gpmc_ad1	mmc1_dat1						gpio1_1	33	P8_24
P8_25	0x800	gpmc_ad0	mmc1_dat0						gpio1_0	32	P8_25
P8_26	0x87C	gpmc_csn0							gpio1_29	61	P8_26
P8_27	0x8E0	lcd_vsync	gpmc_a8	gpmc_a1	pr1_edio_data_in2	pr1_edio_data_out2	pr1_pru1_pru_r30_8	pr1_pru1_pru_r31_8	gpio2_22	86	P8_27
P8_28	0x8E8	lcd_pclk	gpmc_a10	pr1_mii0_crs	pr1_edio_data_in4	pr1_edio_data_out4	pr1_pru1_pru_r30_10	pr1_pru1_pru_r31_10	gpio2_24	88	P8_28
P8_29	0x8E4	lcd_hsync	gpmc_a9	gpmc_a2	pr1_edio_data_in3	pr1_edio_data_out3	pr1_pru1_pru_r30_9	pr1_pru1_pru_r31_9	gpio2_23	87	P8_29
P8_30	0x8EC	lcd_ac_bias_en	gpmc_a11	pr1_mii1_crs	pr1_edio_data_in5	pr1_edio_data_out5	pr1_pru1_pru_r30_11	pr1_pru1_pru_r31_11	gpio2_25	89	P8_30
P8_31	0x8D8	lcd_data14	gpmc_a18	eQEP1_index	mcasp0_axr1	uart5_rxd	pr1_mii_mr0_clk	uart5_ctsn	gpio0_10	10	P8_31
P8_32	0x8DC	lcd_data15	gpmc_a19	eQEP1_strobe	mcasp0_ahclkx	mcasp0_axr3	pr1_mii0_rxdv	uart5_rtsn	gpio0_11	11	P8_32
P8_33	0x8D4	lcd_data13	gpmc_a17	eQEP1B_in	mcasp0_fsr	mcasp0_axr3	pr1_mii0_rxer	uart4_rtsn	gpio0_9	9	P8_33
P8_34	0x8CC	lcd_data11	gpmc_a15	ehrpwm1B	mcasp0_ahclkr	mcasp0_axr2	pr1_mii0_rxd0	uart3_rtsn	gpio2_17	81	P8_34
P8_35	0x8D0	lcd_data12	gpmc_a16	eQEP1A_in	mcasp0_aclkr	mcasp0_axr2	pr1_mii0_rxlink	uart4_ctsn	gpio0_8	8	P8_35
P8_36	0x8C8	lcd_data10	gpmc_a14	ehrpwm1A	mcasp0_axr0		pr1_mii0_rxd1	uart3_ctsn	gpio2_16	80	P8_36
P8_37	0x8C0	lcd_data8	gpmc_a12	ehrpwm1_tripzone_input	mcasp0_aclkx	uart5_txd	pr1_mii0_rxd3	uart2_ctsn	gpio2_14	78	P8_37
P8_38	0x8C4	lcd_data9	gpmc_a13	ehrpwm0_synco	mcasp0_fsx	uart5_rxd	pr1_mii0_rxd2	uart2_rtsn	gpio2_15	79	P8_38
P8_39	0x8B8	lcd_data6	gpmc_a6	pr1_edio_data_in6	eQEP2_index	pr1_edio_data_out6	pr1_pru1_pru_r30_6	pr1_pru1_pru_r31_6	gpio2_12	76	P8_39
P8_40	0x8BC	lcd_data7	gpmc_a7	pr1_edio_data_in7	eQEP2_strobe	pr1_edio_data_out7	pr1_pru1_pru_r30_7	pr1_pru1_pru_r31_7	gpio2_13	77	P8_40
P8_41	0x8B0	lcd_data4	gpmc_a4	pr1_mii0_txd1	eQEP2A_in		pr1_pru1_pru_r30_4	pr1_pru1_pru_r31_4	gpio2_10	74	P8_41
P8_42	0x8B4	lcd_data5	gpmc_a5	pr1_mii0_txd0	eQEP2B_in		pr1_pru1_pru_r30_5	pr1_pru1_pru_r31_5	gpio2_11	75	P8_42
P8_43	0x8A8	lcd_data2	gpmc_a2	pr1_mii0_txd3	ehrpwm2_tripzone_input		pr1_pru1_pru_r30_2	pr1_pru1_pru_r31_2	gpio2_8	72	P8_43
P8_44	0x8AC	lcd_data3	gpmc_a3	pr1_mii0_txd2	ehrpwm0_synco		pr1_pru1_pru_r30_3	pr1_pru1_pru_r31_3	gpio2_9	73	P8_44
P8_45	0x8A0	lcd_data0	gpmc_a0	pr1_mii_mt0_clk	ehrpwm2A		pr1_pru1_pru_r30_0	pr1_pru1_pru_r31_0	gpio2_6	70	P8_45
P8_46	0x8A4	lcd_data1	gpmc_a1	pr1_mii0_txen	ehrpwm2B		pr1_pru1_pru_r30_1	pr1_pru1_pru_r31_1	gpio2_7	71	P8_46
P8 Pin	Offset	mode0	mode1	mode2	mode3	mode4	mode5	mode6	mode7	GPIO #	P8 Pin

The Beaglebone Black P9 Header PinMux Modes

The table below lists the PinMux modes for the pins exposed on the P9 Header. A downloadable and printable pdf version of this information is also available.

P9 Pin	Offset	mode0	mode1	mode2	mode3	mode4	mode5	mode6	mode7	GPIO #	P9 Pin.
P9_1	GND										P9_1
P9_2	GND										P9_2
P9_3	3.3V										P9_3
P9_4	3.3V										P9_4
P9_5	VDD_5V										P9_5
P9_6	VDD_5V										P9_6
P9_7	SYS_5V										P9_7
P9_8	SYS_5V										P9_8
P9_9	PWR_BUT										P9_9
P9_10		Reset_Out									P9_10
P9_11	0x870	gpmc_wait0	gmii2_crs	gpmc_csn4	rmii2_crs_dv	mmc1_sdcd	pr1_mii1_col	uart4_rxd	gpio0_30	30	P9_11
P9_12	0x878	gpmc_be1n	gmii2_col	gpmc_csn6	mmc2_dat3	gpmc_dir	pr1_mii1_rxlink	mcasp0_aclkr	gpio1_28	60	P9_12
P9_13	0x874	gpmc_wpn	gmii2_rxerr	gpmc_csn5	rmii2_rxerr	mmc2_sdcd	pr1_mii1_txen	uart4_txd	gpio0_31	31	P9_13
P9_14	0x848	gpmc_a2	gmii2_txd3	rgmii2_td3	mmc2_dat1	gpmc_a18	pr1_mii1_txd2	ehrpwm1A	gpio1_18	50	P9_14
P9_15	0x840	gpmc_a0	gmii2_txen	rgmii2_tctl	rmii2_txen	gpmc_a16	pr1_mii_mt1_clk	ehrpwm1_tripzone_input	gpio1_16	48	P9_15
P9_16	0x84C	gpmc_a3	gmii2_txd2	rgmii2_td2	mmc2_dat2	gpmc_a19	pr1_mii1_txd1	ehrpwm1B	gpio1_19	51	P9_16
P9_17	0x95C	spi0_cs0	mmc2_sdwp	I2C1_SCL	ehrpwm0_synci	pr1_uart0_txd	pr1_edio_data_in1	pr1_edio_data_out1	gpio0_5	5	P9_17
P9_18	0x958	spi0_d1	mmc1_sdwp	I2C1_SDA	ehrpwm0_tripzone_input	pr1_uart0_rxd	pr1_edio_data_in0	pr1_edio_data_out0	gpio0_4	4	P9_18
P9_19	0x97C	uart1_rtsn	timer5	dcan0_rx	I2C2_SCL	spi1_cs1	pr1_uart0_rts_n	pr1_edc_latch1_in	gpio0_13	13	P9_19
P9_20	0x978	uart1_ctsn	timer6	dcan0_tx	I2C2_SDA	spi1_cs0	pr1_uart0_cts_n	pr1_edc_latch0_in	gpio0_12	12	P9_20
P9_21	0x954	spi0_d0	uart2_txd	I2C2_SCL	ehrpwm0B	pr1_uart0_rts_n	pr1_edio_latch_in	EMU3	gpio0_3	3	P9_21
P9_22	0x950	spi0_sclk	uart2_rxd	I2C2_SDA	ehrpwm0A	pr1_uart0_cts_n	pr1_edio_sof	EMU2	gpio0_2	2	P9_22
P9_23	0x844	gpmc_a1	gmii2_rxdv	rgmii2_rctl	mmc2_dat0	gpmc_a17	pr1_mii1_txd3	ehrpwm0_synco	gpio1_17	49	P9_23
P9_24	0x984	uart1_txd	mmc2_sdwp	dcan1_rx	I2C1_SCL		pr1_uart0_txd	pr1_pru0_pru_r31_16	gpio0_15	15	P9_24
P9_25	0x9AC	mcasp0_ahclkx	eQEP0_strobe	mcasp0_axr3	mcasp1_axr1	EMU4	pr1_pru0_pru_r30_7	pr1_pru0_pru_r31_7	gpio3_21	117	P9_25
P9_26	0x980	uart1_rxd	mmc1_sdwp	dcan1_tx	I2C1_SDA		pr1_uart0_rxd	pr1_pru1_pru_r31_16	gpio0_14	14	P9_26
P9_27	0x9A4	mcasp0_fsr	eQEP0B_in	mcasp0_axr3	mcasp1_fsx	EMU2	pr1_pru0_pru_r30_5	pr1_pru0_pru_r31_5	gpio3_19	115	P9_27
P9_28	0x99C	mcasp0_ahclkr	ehrpwm0_synci	mcasp0_axr2	spi1_cs0	eCAP2_in_PWM2_out	pr1_pru0_pru_r30_3	pr1_pru0_pru_r31_3	gpio3_17	113	P9_28
P9_29	0x994	mcasp0_fsx	ehrpwm0B		spi1_d0	mmc1_sdcd	pr1_pru0_pru_r30_1	pr1_pru0_pru_r31_1	gpio3_15	111	P9_29
P9_30	0x998	mcasp0_axr0	ehrpwm0_tripzone_input		spi1_d1	mmc2_sdcd	pr1_pru0_pru_r30_2	pr1_pru0_pru_r31_2	gpio3_16	112	P9_30
P9_31	0x990	mcasp0_aclkx	ehrpwm0A		spi1_sclk	mmc0_sdcd	pr1_pru0_pru_r30_0	pr1_pru0_pru_r31_0	gpio3_14	110	P9_31
P9_32	VADC										P9_32
P9_33		AIN4									P9_33
P9_34	AGND										P9_34
P9_35		AIN6									P9_35
P9_36		AIN5									P9_36
P9_37		AIN2									P9_37
P9_38		AIN3									P9_38
P9_39		AIN0									P9_39
P9_40		AIN1									P9_40
P9_41	0x9B4	xdma_event_intr1		tclkin	clkout2	timer7	pr1_pru0_pru_r31_16	EMU3	gpio0_20	20	P9_41
P9_41.1	0x9A8	mcasp0_axr1	eQEP0_index		mcasp1_axr0	EMU3	pr1_pru0_pru_r30_6	pr1_pru0_pru_r31_6	gpio3_20	116	P9_41.1
P9_42	0x964	eCAP0_in_PWM0_out	uart3_txd	spi1_cs1	pr1_ecap0_ecap_capin_apwm_o	spi1_sclk	mmc0_sdwp	xdma_event_intr2	gpio0_7	7	P9_42
P9_42.1	0x9A0	mcasp0_aclkr	eQEP0A_in	mcasp0_axr2	mcasp1_aclkx	mmc0_sdwp	pr1_pru0_pru_r30_4	pr1_pru0_pru_r31_4	gpio3_18	114	P9_42.1
P9_43	GND										P9_43
P9_44	GND										P9_44
P9_45	GND										P9_45
P9_46	GND										P9_46
P9 Pin	Offset	mode0	mode1	mode2	mode3	mode4	mode5	mode6	mode7	GPIO #	P9 Pin.

License

The contents of this web page are provided "as is" without any warranty of any kind and without any claim to accuracy. Please be aware that the information provided may be out-of-date, incomplete, erroneous or simply unsuitable for your purposes. Any use you make of the information is entirely at your discretion and any consequences of that use are entirely your responsibility. All source code is provided under the terms of the MIT License.

Acknowledgements

Various internet resources were used to help understand the workings of the Beaglebone Black. Especially useful were Derek Molloys Beaglebone pages. Thank you Derek!.